Manufacturing features of semiconductor devices at a minimum feature size may increasingly be necessary to achieve product competitiveness, which is often dependent on device density and overall chip size in modern semiconductor processing. For sub-100 nm advanced semiconductor processes in particular, contact/via resistance due to misalignment involving metal features of such minimum feature size may be a serious concern. Even with processing techniques that may help improve reliability, such as optical proximity correction (OPC), a final size of the metal features may have relatively large variations due to intrinsic semiconductor processing overlay issues, resulting in misalignment between layers and increased resistance at an interface between contacts/vias and the metal features of such minimum feature size.
FIG. 1 shows a top or layout view 100 of a conventional structure comprising metal features. A metal layer can include a plurality of long metal lines 102 in one area and smaller metal features 110 (e.g., so-called “pads” having a minimum feature size) in another area as shown. When vias 104 are arranged to be connected to such long metal lines 102 and such metal features 110, misalignment 106 can occur between the vias 104 and the metal features 110 as shown.
FIG. 2 shows a cross-sectional view 200 (along dashed line A-A′) of the conventional structure of FIG. 1, including interlayer dielectric (ILD) 112 for isolating the metal lines 102 from overlying metal lines (not shown) that connect to metal lines 102 and metal features 110 through vias 104. In FIG. 2, underlying contacts/vias 108 below the metal lines 102 and metal features 110 may also be misaligned relative to the metal lines 102 and metal features 110, consistent with FIG. 1.